1. Field of the Invention
The present invention relates to a solid image pick-up apparatus, a camera and an information processing apparatus having the solid image pick-up apparatus.
2. Description of the Related Art
General-solid image pick-up apparatuses, e.g., a line sensor and an area sensor, have a large number of sensor cells including photoelectric converting devices with a line alignment or two-dimensional alignment. Outputs from the sensor cells are temporarily held by holding capacitances and thereafter are distributed onto a common signal line via a transistor switch. Thus, a potential on the common signal line is changed, it amplified by an amplifier and then outputted.
The common signal line has not only a wiring capacitance as a parasitic capacitance but also a parasitic capacitance corresponding to a drain capacitance of the number of the transistor switches corresponding to the number of line sensors in the line direction because the number of the transistors for the switch corresponding to the number of sensor cells in the line direction is connected to the common signal line.
The increase in parasitic capacitance of the common signal line reduces potential change of the common signal line upon distributing charges held in the holding capacitance to the common signal line. In recent years, the increase in number of pixels and in size of the solid image pick-up apparatuses has advanced and, in accordance therewith, the increase in the number of the transistor switches (in the total source capacitance) and the increase in wiring capacitances allow the parasitic capacitance of the common signal line to become higher.
A photoelectrically converting apparatus to solve the above-mentioned problems is disclosed in Japanese Unexamined Patent Application Publication No. 2-268063. FIG. 1 is a diagram showing the structure of the above-mentioned photoelectrically converting apparatus. Referring to FIG. 1, the photoelectrically converting apparatus comprises two photoelectrically converting devices S1 and S2 and a single MOS transistor TH1 corresponding thereto. Therefore, the total number of MOS transistors connected to a common output signal line SL is half of the number of columns and thus a parasitic capacitance of the common output signal line SL is reduced. The photoelectric converting devices S1 and S2 are connected to a signal line H1 via MOS transistors Ts1 and Ts2. Outputs from the photoelectrically converting devices S1 and S2 charge to capacitors C1 and C2 commonly connected to the signal line H1, and are sequentially distributed onto the output signal line SL via the MOS transistor TH1.
However, in the above-mentioned conventional photoelectrically converting device, the capacitors C1 and C2 having holding capacitances are commonly connected to the signal line H1. Thus, although the parasitic capacitance of the output signal line SL is reduced, the parasitic capacitance of the signal line H1 is increased. Such a disadvantage exerts little undesirable-influence on the operation of the device when the number of capacitors commonly connected to the signal line H1 is decreased. It becomes more serious, however, as the number of capacitors commonly connected to the signal line H1 is increased. This means that, unpreferably, there is an increase in load to be driven by the photoelectrically converting devices S1 and S2. A positional relationship between the capacitor C1 and the photoelectrically converting device S1 cannot be similar to that between the capacitor C2 and the photoelectrically converting device S2. Consequently, a route for reading the signal from the photoelectric converting device S1 cannot match a route for reading the signal from the photoelectric converting device S2.